A number of integrated circuit chips are arranged in a matrix on a semiconductor wafer (referred to as a “wafer” hereinafter) subjected to a series of fabrication processes. These elements are separated into individual elements by a conventional dicing method as shown in FIG. 13. That is, a holder 10 obtained by adhering an adhesive layer (e.g., an adhesive film 12 (e.g., 100 to 200 μm) having an adhesive upper surface 12a) to one surface of a ring-like frame 11 larger than the size of a wafer W is used. The holder 10 having the wafer W adhered to the adhesive surface 12a of the adhesive film 12 is placed on a chuck table 13. By moving a rotating blade 14 along scribe lines defining individual integrated circuit chips C, elements C are separated (for the sake of convenience, the integrated circuit chips and chips are denoted by the same reference symbol “C”). The holder 10 is unloaded from the chuck table 13. In positions corresponding to the individual chips C, the chips C are peeled one by one from the adhesive film 12 as they are pushed up from the lower surface of the adhesive film by a pushing means. A handling apparatus transports the peeled chips to the next step.
There are a case in which the electrical characteristics of the separated chips C are tested, and a case in which the chips C are directly mounted without attaching any lead frames. In these cases, the chips C are loaded one by one into a testing apparatus by the handling apparatus, and tested.
In the case in which the chips C separated from the wafer W are tested without attaching any lead frames, it is advantageous in respect of the efficiency of testing or the like to collectively (simultaneously) probe a plurality of chips C adhered to the adhesive film 12, i.e., a plurality of diced chips C. In the dicing step, however, a cutting blade 14 cuts into the middle of the adhesive film 12. In this state, the relative positions of the chips C shift from each other by a maximum of a few hundred μm, and this positional shift is irregular. This presumably occurs because the wafer W is adhered while tension is applied to the adhesive film 12, so a cut portion of the adhesive film 12 deforms since the portion is not supported by the wafer any longer.
For this reason, a plurality of diced chips cannot be collectively (simultaneously) probed.
Since this increases the total testing time or the like, the testing efficiency decreases. Also, the handling apparatus easily causes trouble when handling small chips of about 1.5 mm square.
The present invention has been developed under the circumstances described above. The present invention provides a dicing method and testing method capable of increasing the efficiency of testing of integrated circuit chips, and a substrate holding apparatus and adhesive film usable in these methods.
In addition, although a so-called double-coated tape is well known, no technique of extending its applications by giving a difference between the adhesion properties of the two surfaces is known.